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DVB-S2 demodulator (CMS0014)
v0.5.7: June, 2009
- Extended symbol rate range by 2 octaves to support 128kbd from 30MHz master clock.
- Added synthesis option to improve external-gain control algorithm at expense of design-size.
- Increased pipelining around PLL engine to ease PAR congestion.
- Updated Modelsim libraries to v6.4a.
v0.4.0: November, 2007
- Added serial-DAC AGC gain control.
- Extended range on XGC gain output signal.
v0.3.8: October, 2007
- Removed some synthesis attribute warnings reported in Quartus 7.1.
- Removed M-RAM constraints to allow Quartus to choose RAM targets automatically.
- Added release notes to megacore installation dialogs.
- Fixed megacore modelsim library generation bug that prevented post v6.2 simulation.
v0.3.6: May, 2007
- Embedded shortcut links within the PDF documentation.
- Re-built with updated datasheets.
v0.3.4: February, 2007
- Consolidated build libraries to simplify end implementation.
v0.3.0: January, 2007
- Synthesis tweaks to improve stratix2-5 performance.
v0.2.4: November, 2006
- Added modelsim libraries.
v0.2.2: October, 2006
- Added spectral inversion operation.
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Block diagram