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ATSC 8-VSB modulator (CMS0033)

v0.3.5: October, 2008

  • Various speed improvements and increased pipelining.

v0.3.4: September, 2008

  • Optimised aspect-ratio of PCR RAM.
  • Reduced FIFO width to improved QOR in Altera devices.

v0.3.2: August, 2008

  • Documentation update.

v0.3.1: August, 2008

  • Datapath optimisation and QOR improvements.

v0.3.0: August, 2008

  • Replaced wheat_pack with general purpose cms0033_config package.

v0.2.9: August, 2008

  • Fixed quartus synthesis translation problem.

v0.2.6: August, 2008

  • Corrected PCR synthesis bug.

v0.2.5: July, 2008

  • Replaced multiple TS interrupts with a general purpose TS interrupt.
  • Improved the robustness of auto TS-resync.

v0.2.4: July, 2008

  • Add auto re-sync to FEC interleaver.

v0.2.2: June, 2008

  • Improved FEC interleaving performance.
  • Added TS buffer reset control bits.

v0.1.9: June, 2008

  • Fixed occasional spectral-inversion issue when using the software-reset bit.

v0.1.7: June, 2008

  • Re-worked code to work-around a synplify-pro synthesis bug.
  • Added CycloneIII Starter Kit board example.

v0.1.6: April, 2008

  • Removed explicit use M-RAM option when targetting Altera Stratix families.

v0.1.4: April, 2008

  • Modified PCR block to improve Cyclone3 support.

v0.1.3: April, 2008

  • Multi-channel speed improvements.

v0.1.2: April, 2008

  • Added multi-channel option.

v0.1.1: April, 2008

  • Updated component declaration bug.
  • Modified AD9857 interrupt to only occur when the ready-flag is de-asserted.
  • Added force NULL TS packet register-field.
  • Added sync-found interrupts.
  • Increased update-rate for the TS calculation registers.

v0.1.0: March, 2008

  • Increased pipelining through the interleaver sections.
  • Corrected possible lock-up issue when using the RDY/VALID interface.

v0.0.9: March, 2008

  • Corrected occasional AD9857 start-up mis-alignment.

v0.0.8: March, 2008

  • Added SOPC builder support.
  • Added AD9857 support.

v0.0.5: February, 2008

  • Fixed failing software reset issue.
  • Documentation updates.

v0.0.4: February, 2008

  • Corrected a mis-assignment error for the TS input and TS output calculation registers.

v0.0.3: February, 2008

  • Added parameterisation megacore GUI dialogs.
  • Added single-clock source re-sampling filter.
  • Added PCR re-stamping plug-in.
  • Added Modelsim compilation libraries.

v0.0.1: February, 2008

  • Initial build.
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